Most modern computer systems include at least one processor for processing computer instructions and a main memory system that stores the instructions and data processed by the processor. The main memory system is generally implemented with some form of Dynamic Random Access Memory generally known as DRAM. DRAM devices have a very high memory density (amount of data stored per area of integrated circuit used), low power usage, and a relative inexpensive cost. Thus, DRAM devices are used to construct large main memory systems for computer systems.
The speed at which computer processors operate has been continually increasing. Specifically, decreasing the size of the semiconductor transistors and decreasing the operating voltages of these transistors has allowed processor clocks to run at faster rates. However, the performance of DRAM main memory systems that provide data to these faster processors have not kept pace with the increasingly faster processors. Thus, DRAM based main memory systems have become a bottleneck for computer performance. To mitigate this issue, larger Static Random Access Memory (SRAM) based cache memory systems are often used. SRAM devices operate at much faster rates than DRAM devices but have a lower memory density, consume more power, and are more expensive. Furthermore, cache memory systems only provide a speed improvement when a cache “hit” occurs (the needed data is available in the cache memory system). When a cache miss occurs, data must be fetched from the lower speed DRAM memory system. In some applications that require a guaranteed fast performance, the use of cache memory system will not suffice. Thus, it is desirable to improve the speed of memory systems such that memory systems can handle memory read and write operations as fast as possible.